Inline-type wafer conveyance device

ABSTRACT

A structure is provided in which a load lock chamber ( 51 ) for carrying in an unprocessed wafer from outside and carrying out a processed wafer to outside, a first end conveyance chamber ( 54   a ) to be connected to the load lock chamber, at least one intermediate conveyance chamber ( 54   b ), a plurality of sets of a pair of process modules ( 52   a,    52   b ) provided adjacent to each other and capable of independent processing, and a second end conveyance chamber ( 54   c ) disposed at the end part on the opposite side of the load lock chamber are connected in series. Each set of process modules ( 52   a,    52   b,    52   c  and  52   d ) is arranged one by one between the first end conveyance chamber and the intermediate conveyance chamber, between the intermediate conveyance chambers, and between the intermediate conveyance chamber and the second end conveyance chamber, respectively.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application is a continuation application of International Application No. PCT/JP2007/071817, filed on Nov. 9, 2007, the entire contents of which are incorporated by reference herein.

TECHNICAL FIELD

The present invention relates to a semiconductor manufacturing device and a manufacturing method and, in more detail, relates to an inline-type wafer conveyance device having a compact structure.

BACKGROUND ART

There are several types of conventional semiconductor wafer conveyance devices and each of them has a big drawback. A conventional cluster-type wafer conveyance device has a structure in which a plurality of process modules is arranged radially around a robot chamber located in the center. Such a cluster-type wafer conveyance device requires a large footprint for installation. Further, each time processing in each process module is completed, a wafer is temporarily placed in a buffer part etc. and waits for the next processing, and therefore, the processing speed of the device as a whole is relatively slow. Further, in most cases, the maximum number of process modules in a cluster-type wafer conveyance device is normally limited to five or six for design reasons.

An inline-type wafer conveyance device has a higher processing speed compared to that of a cluster-type device. However, because of its rectilinear structure, it is hard to adapt the inline-type wafer conveyance device to the structure of a most recent semiconductor manufacturing facility. Further, in a conventional inline-type wafer conveyance device, when a wafer is conveyed in a vacuum environment in a semiconductor manufacturing process, there may be a case where particles occur at an unacceptable level due to the friction between the components of the waver conveyance device.

A plan view of a conventional inline-type wafer conveyance device is shown in FIG. 1 (for example, refer to patent document 1). In a wafer conveyance device 10, each of process modules 13 a to 13 g is arranged adjacent to each other and connected in an inline manner. Each process module is separated by a gate valve (not shown schematically). A wafer is conveyed from a load chamber 14 to the first process module 13 a by a robot 12 within a robot chamber 11 and is processed sequentially in each process module. The processed wafer is conveyed from the last process module 13 g to an unload chamber 15 by the robot 12. Extra robots to convey a wafer or robot chambers are not necessary, and therefore, a footprint required in the wafer conveyance device 10 is comparatively small.

A partial section view of the inline-type wafer conveyance device 10 shown in FIG. 1 is shown in FIG. 2. A wafer 21 is mounted on a carrier 23 and conveyed from a certain process module to the next process module. In each process module, the wafer 21 is lifted from the carrier 23 by a lift base 26 and processed, and then is mounted on the carrier 23 again and conveyed to the next process module. The carrier 23 is moved by means of a transfer mechanism, such as a roller 25. When the wafer 21 is conveyed to the next neighboring process module, a gate valve 24 is opened and thus the neighboring process modules are brought into a state where they are not hermetically sealed from each other. The wafer 21 having been subjected to processing in a certain process module waits until the next process module becomes empty.

A plan view of another conventional inline-type wafer conveyance device 30 is shown in FIG. 3 (for example, refer to patent document 2). The wafer conveyance device 30 comprises two front opening unified pods (FOUP) 31 a and 31 b. For example, the FOUP 31 a has two load chambers 32 a and 32 b each having a cassette for storing an unprocessed wafer and the FOUP 31 b has two unload chambers 33 a and 33 b each having a cassette for storing a processed wafer. The wafer conveyance device 30 further comprises buffer chambers 36 a to 36 d for temporarily placing a wafer during its conveyance. At the time of processing, a wafer is conveyed from a cassette within the load chamber 32 a or 32 b to the first buffer chamber 36 a by a robot 35 a within a robot chamber 34 a. As shown schematically, the wafer conveyance device 30 comprises robot chambers 38 a to 38 c between the buffer chambers. Between each buffer chamber and its neighboring robot chamber, and between each robot chamber and its neighboring process module, a gate valve 39 is provided as shown schematically. A wafer once placed in the buffer chamber 36 a is conveyed to a first process module 37 a by a robot within the robot chamber 38 a and processed therein. Subsequently, the wafer is conveyed to a second process module 37 b again by the robot within the robot chamber 38 a and processed therein. The wafer having been subjected to the processing in the second process module 37 b is placed in the second buffer chamber 36 b by the robot within the robot chamber 38 a. Further, the wafer is conveyed from the buffer chamber 36 b to a third process module 37 c by the robot within the second robot chamber 38 b. After that, the wafer is similarly moved from the process module 37 c to a process module 37 f sequentially and processed therein. The wafer having been subjected to the processing in all of the process modules is once placed in the buffer chamber 36 d and then stored in the cassette within the unload chamber 33 a or 33 b of the FOUP 31 b by a robot 35 b within a robot chamber 34 b. The wafer conveyance device 30 has an advantage that the number of the process modules can be increased flexibly as needed.

A plan view of a conventional cluster-type wafer conveyance device is shown in FIG. 4 (for example, refer to patent document 3). A wafer conveyance device 40 comprises an inlet module 45 a and an outlet module 45 b through which a wafer 46 is carried in from and carried out to outside, conveyance chambers 42 a and 42 b for conveying a wafer to process modules 41 b, 41 c, 41 f and 41 g, and conveyance robots 43 a and 43 b provided within the conveyance chambers 42 a and 42 b. A main controller 47 is communicated with each process module controller P, the inlet module 45 a and the outlet module 45 b, and an operator control panel via a standard communication bus 48. The wafer 46 not processed yet within the inlet module 45 a is once placed on an aligner 44 by the conveyance robot 43 a within the conveyance chamber 42 a and its orientation is adjusted on the aligner 44. Then, the wafer on the aligner 44 is conveyed to, for example, the process module 41 b or 41 c by the conveyance robot 43 a or 43 b and processed therein, and then returned onto the aligner 44 again. After such a task is repeated, the wafer having been subjected to the processing in the process modules 41 b, 41 c, 41 f and 41 g is returned to the outlet module 45 b by the conveyance robot 43 a.

-   [Patent document 1] United States Patent Application Publication No.     2006/0102078 Specification -   [Patent document 2] U.S. Pat. No. 7,210,246 Specification -   [Patent document 3] Japanese Publication of Patent Application No.     HEI 1-500072

SUMMARY OF THE INVENTION

It is required, however, for the inline-type wafer conveyance device 10 shown in FIG. 1 and FIG. 2 to comprise the mobile carrier 23 capable of holding a wafer to be processed within the wafer conveyance device 10 and a transfer mechanism, such as the roller 25, for moving the carrier 23. In this case, a problem arises that the structure of the wafer conveyance device 10 becomes complicated and expensive. Further, the carrier 23 is moved on a transfer mechanism, such as the roller 25, and therefore, particles are likely generated due to friction between these components. Particles that stick to the wafer 21 conveyed within the wafer conveyance device 10, degrade the quality of a film formed on the wafer.

The conventional inline-type wafer conveyance device 30 shown in FIG. 3 requires the buffer chambers 36 a to 36 d for temporarily placing a wafer, such that the device becomes more complicated. Further, the footprint required by the wafer conveyance device 30 becomes larger due to these buffer chambers. Furthermore, if an attempt is made to realize the wafer conveyance device 30 without using the buffer chambers 36 a to 36 d, it becomes necessary to directly deliver, for example, a wafer having been subjected to the processing in the second process module 37 b from the robot chamber 38 a to the next robot chamber 38 b. That is, it becomes necessary to deliver a wafer between the robots. If such a structure is employed, the precision and reliability of the operation of the wafer conveyance device 30 are degraded.

The conventional cluster-type wafer conveyance device 40 has a structure in which the process modules are arranged radially with the conveyance chambers 42 a and 42 b located in the center as a center, and therefore, a problem arises that its footprint is large. Further, with the cluster-type wafer conveyance device 40, it is necessary to once place a wafer on the aligner 44 before conveying the wafer to each process module. The necessity of such an aligner causes the footprint of the whole device to further increase. Then, each time processing is completed, the wafer needs to be placed on the aligner 44, and therefore, a complicated conveying task is required.

In order to solve the conventional problems described above, an object of the present invention is to realize an inline-type wafer conveyance device capable of suppressing the generation of particles, obviating a complicated conveyance mechanism, and having a simple configuration with a small footprint.

In order to achieve the above-mentioned object, an inline-type wafer conveyance device according to the present invention has a structure in which a load lock chamber for carrying in an unprocessed wafer from outside and carrying out a processed wafer to outside, a first end conveyance chamber connected to the load lock chamber, at least one intermediate conveyance chamber, a plurality of sets of a pair of process modules provided adjacent to each other and capable of independent processing, and a second end conveyance chamber disposed at the end part on the opposite side of the load lock chamber are connected in series. Each of the sets of process modules is arranged one by one between the first end conveyance chamber and the intermediate conveyance chamber, between the intermediate conveyance chambers, and between the intermediate conveyance chamber and the second end conveyance chamber.

The first end conveyance chamber, the intermediate conveyance chamber and the second end conveyance chamber may have a conveyance mechanism capable of simultaneously conveying at least two wafers.

It may also be possible to configure the first end conveyance chamber and the second end conveyance chamber so as to each have at least one conveyance mechanism and first and second side surfaces perpendicular to each other. It may also be possible to configure each of the intermediate conveyance chambers so as to have at least one conveyance mechanism, substantially a square plane shape, and four side surfaces. It may also be possible to configure each of the process modules so as to have at least first and second side surfaces perpendicular to each other.

In this case, the first and second side surfaces of the first end conveyance chamber are connected to the first side surface of one of the process modules constituting the first set of process modules and to the first side surface of the other process module, respectively. The first and second side surfaces of each intermediate conveyance chamber are connected to the second side surface of one of the process modules of the set of process modules located immediately ahead and to the second side surface of the other process module, respectively. Third and fourth side surfaces of each intermediate conveyance chamber are connected to the first side surface of one of the process modules of the set of process modules located immediately behind and to the first side surface of the other process module, respectively. The first and second side surfaces of the second end conveyance chamber are connected to the second side surface of one of the process modules of the set of process modules located immediately ahead and to the second side surface of the other process module, respectively.

It is possible to configure the conveyance chamber and the process module so as to have various plane shapes, such as a square and a circle, and the side surfaces configured as described above are not necessarily required. It is possible to configure a pair of process modules belonging to each set of process modules so as to be connected to one of neighboring conveyance chambers via one of two gate valves the directions of which are perpendicular to each other and to the other neighboring conveyance chamber via the other gate valve.

The first and second side surfaces of the first end conveyance chamber, the first to fourth side surfaces of the intermediate conveyance chamber, the first and second side surfaces of the second end conveyance chamber, and the first and second side surfaces of the process module may include a horizontal slit to let a wafer pass, respectively. Further, the process module may have a stage to place a wafer.

In the above-described structure in which the intermediate conveyance chamber has substantially a square plane shape, if the total number of the first end conveyance chamber, the intermediate conveyance chambers and the second end conveyance chamber is assumed to be m, the maximum number of the process modules n is expressed as n=2(m−1).

The load lock chamber, the first end conveyance chamber, the intermediate conveyance chamber, the process module and the second end conveyance chamber are connected via gate valves.

The load lock chamber may include a conveyance mechanism and first and second buffer chambers. In this case, the first end conveyance chamber is configured so as to have substantially a square plane shape and four side surfaces. The third and fourth side surfaces of the first end conveyance chamber are connected to the first and second buffer chambers, respectively. An unprocessed wafer is carried into one of the process modules connected to the first end conveyance chamber from the first buffer chamber by the conveyance mechanism of the first end conveyance chamber. A processed wafer is carried out to the second buffer chamber from the other process module connected to the first end conveyance chamber by the conveyance mechanism of the first end conveyance chamber. Even when the first end conveyance chamber has a circular plane shape or a plane shape other than a square, it is only required to connect the first end conveyance chamber to each of the first and second buffer chambers of the load lock chamber.

According to the present invention, an inline-type wafer conveyance device is realized, which is capable of suppressing the generation of particles, obviates a complicated conveyance mechanism, and has s small footprint.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of a conventional inline-type wafer conveyance device.

FIG. 2 is a partial section view of the conventional inline-type wafer conveyance device shown in FIG. 1.

FIG. 3 is a plan view of another conventional inline-type wafer conveyance device.

FIG. 4 is a plan view of a conventional cluster-type wafer conveyance device.

FIG. 5 is a plan view of an inline-type wafer conveyance device of the present invention.

FIG. 6 is a plan view of an embodiment of an inline-type wafer conveyance device according to the present invention.

FIG. 7 is a plan view of another structure example of an inline-type wafer conveyance device according to the present embodiment.

FIG. 8 is a diagram showing a structure example when a specific process is performed in a structure similar to that of the wafer conveyance device in FIG. 6.

FIG. 9 is a diagram showing a structure example when the number of process modules and intermediate conveyance chambers is increased in a structure similar to that of the wafer conveyance device in FIG. 7.

FIG. 10 is a diagram showing a specific example of a structure similar to that of the wafer conveyance device in FIG. 6.

FIG. 11 is a diagram showing a case where an actual process is performed using the inline-type wafer conveyance device in the present embodiment similar to that described in FIG. 7.

FIG. 12 is a diagram showing a case where an actual process is performed after adding further two process modules and one intermediate conveyance chamber to the inline-type wafer conveyance device illustrated in FIG. 11.

FIG. 13 is a diagram showing a case where an actual process is performed using an inline-type wafer conveyance device similar to that in FIG. 12.

FIG. 14 is a diagram showing a case where an actual process is performed using an inline-type wafer conveyance device like that illustrated in FIG. 10.

FIG. 15 is a diagram showing a case where an actual process is performed using an inline-type wafer conveyance device similar to that in FIG. 14.

FIG. 16 is a diagram showing a case where an actual process is performed using an inline-type wafer conveyance device similar to that in FIG. 14.

FIG. 17 is a diagram showing a case where an actual process is performed using an inline-type wafer conveyance device similar to that in FIG. 14.

FIG. 18 is a diagram showing a case where an actual process is performed using an inline-type wafer conveyance device similar to that in FIG. 14.

FIG. 19 is a diagram showing a case where an actual process is performed using an inline-type wafer conveyance device having the structure illustrated in FIG. 14 in which the number of process modules is eight and the number of intermediate conveyance chambers is three.

FIG. 20 is a graph showing a comparison of a relationship of throughput and processing time of a wafer conveyance device, between when the second end conveyance chamber is used as in the wafer conveyance device according to the present invention and when the second end conveyance chamber is not used.

Reference Signs List 10 wafer conveyance device 11 conveyance chamber 12 robot 13a-13g process module 14 load chamber 15 unload chamber 21 wafer 23 carrier 24 gate valve 25 roller 26 lift base 30 wafer conveyance device 31a, 31b FOUP 32a, 32b load chamber 33a, 33b process module 34a, 34b conveyance chamber 35a, 35b robot 36a-36d buffer chamber 37a-37f process module 38a-38c conveyance chamber 39 gate valve 40 wafer conveyance device 41b, 41c, 41f, 41g process module 42a, 42b conveyance chamber 43a, 43b conveyance robot 44 aligner 45a inlet module 45b outlet module 46 wafer 47 main controller 48 standard communication bus 50 wafer conveyance device 51 load lock chamber 52a-52d process module 54a first end conveyance chamber 54b intermediate conveyance chamber 54c second end conveyance chamber 55a-55c conveyance mechanism 56a-56j gate valve 60 wafer conveyance device 61 FOUP 61a load chamber 61b unload chamber 62a-62d process module 64a first end conveyance chamber 64b-64d intermediate conveyance chamber 64e second end conveyance chamber 65a-65e conveyance mechanism 66 gate valve 70 wafer conveyance device 71 load lock chamber 71a load chamber 71b unload chamber 71c conveyance mechanism 71d, 72e buffer chamber 72a-72d process module 74a first end conveyance chamber 74b intermediate conveyance chamber 74c second end conveyance chamber 75a conveyance mechanism 80 wafer conveyance device 81 FOUP 81a load chamber 81b unload chamber 82a-82h process module 84a first end conveyance chamber 84b-84d intermediate conveyance chamber 84e second end conveyance chamber 87 cathode electrode 90 wafer conveyance device 91 load lock chamber 91d, 92e buffer chamber 91f conveyance chamber 92a process module 98 space 100, 110, 120, wafer conveyance device 130, 140, 150, 160, 170, 180, 190 101a, 111a, 121a, load chamber 131a, 141a, 151a, 161a, 171a, 181a, 191a 101b, 111b, 121b, unload chamber 131b, 141b, 151b, 161b, 171b, 181b, 191b 102a-102d, 112a-112d, process module 122a-122f, 132a-132f, 142a-142f, 152a-152j, 162a-162j, 172a-172j, 182a-182j, 192a-192j 105a, 105b arm 107 cathode electrode 114a first end conveyance chamber 115a first wafer holding means 124d second end conveyance chamber 125a conveyance mechanism

BEST MODES FOR CARRYING OUT THE INVENTION

FIG. 5 is a plan view of an inline-type wafer conveyance device of the present invention. A wafer conveyance device 50 comprises a load lock chamber 51, a first end conveyance chamber 54 a, a set of a first process module 52 a and a second process module 52 b, an intermediate conveyance chamber 54 b, a set of a third process module 52 c and a fourth process module 52 d, and a second end conveyance chamber 54 c. The second end conveyance chamber 54 c is disposed at the end part of the wafer conveyance device 50 on the opposite side of the load lock chamber 51 and no components are disposed beyond that.

The load lock chamber 51 is configured to carry in an unprocessed wafer from outside (atmosphere side) and to carry out a processed wafer to outside (atmosphere side) and includes an evacuation mechanism (not shown schematically). The load lock chamber 51 may include a plurality of load/unload chambers (not shown schematically) configured to carry in an unprocessed wafer from outside (atmosphere side) and to carry out a processed wafer to outside (atmosphere side). In this case, a wafer carried into the process module 52 a using the first end conveyance chamber 55 a from one load/unload chamber is sent to the same load/unload chamber or another load/unload chamber and carried out to outside when processing in each process module is returned to the load lock chamber 51.

The first end conveyance chamber 54 a, the intermediate conveyance chamber 54 b, and the second end conveyance chamber 54 c include conveyance mechanisms 55 a, 55 b and 55 c for conveying a wafer, respectively. The conveyance mechanisms 55 a to 55 c are each configured as a robot having an arm for moving a wafer.

The first end conveyance chamber 54 a is connected to the load lock chamber 51 via gate valves 56 a and 56 b. Between the first end conveyance chamber 54 a and the intermediate conveyance chamber 54 b, a pair of the first process module 52 a and the second process module 52 b is arranged in parallel. The first process module 52 a is connected to the first end conveyance chamber 54 a and the intermediate conveyance chamber 54 b, respectively, via gate valves 56 c and 56 e. The second process module 52 b is connected to the first end conveyance chamber 54 a and the intermediate conveyance chamber 54 b, respectively, via gate valves 56 d and 56 f. The first process module 52 a and the second process module 52 b are configured so as to be capable of processing a wafer independently of each other.

The wafer conveyance device 50 shown in FIG. 5 comprises one intermediate conveyance chamber and two sets of process modules, however, the present embodiment is not limited to this structure. The wafer conveyance device 50 may comprise a plurality of intermediate conveyance chambers and three or more sets of process modules in accordance with a necessary number of processes. That is, between the first end conveyance chamber and the first intermediate conveyance chamber, between the intermediate conveyance chambers, and between the last intermediate conveyance chamber and the second end conveyance chamber, a pair of process modules capable of independent processing is arranged, respectively.

An unprocessed wafer is carried into a load chamber (not shown schematically) of the load lock chamber 51 from outside. The gate valves 56 a and 56 c are opened and the wafer is conveyed from the load lock chamber 51 to the first process module 52 a by the conveyance mechanism 55 a. The gate valves 56 a and 56 c that have been opened are closed and the wafer is processed within the first process module 52 a. When the processing is completed, the gate valves 56 e and 56 g are opened and the wafer is conveyed from the first process module 52 a to the third process module 52 c by the conveyance mechanism 55 b. The gate valves 56 e and 56 g that have been opened are closed and the wafer is processed within the third process module 52 c.

The wafer conveyance device in the present embodiment is characterized by providing the second end conveyance chamber (54 c in FIG. 5), which is connected to the opposite side of the load lock chamber 51 of the last set of process modules (the third process module 52 c and the fourth process module 52 d in FIG. 5). This second end conveyance chamber is located at the end part of the wafer conveyance device.

With this structure, it is made possible to convey a wafer processed in the first process module 52 a and the third process module 52 c as described above to the fourth process module 52 d arranged in parallel with the third process module 52 c by the conveyance mechanism 55 c within the second end conveyance chamber 54 c. In the operation, after gate valves 56 i and 56 j are opened, the conveyance mechanism 55 c moves the wafer within the third process module 52 c to the fourth process module 52 d. The gate valves 56 i and 56 j that have been opened are closed and the wafer is processed within the fourth process module 52 d. When the processing is completed, a gate valve 56 h and the gate valve 56 f are opened and the wafer is conveyed to the second process module 52 b by the conveyance mechanism 55 b. The gate valves 56 h and 56 f that have been opened are closed and the wafer is processed within the second process module 52 b. When the processing is completed, the gate valves 56 d and 56 b are opened and the processed wafer is conveyed to the load lock chamber 51 by the conveyance mechanism 55 a and carried out from the unload chamber (not shown schematically) to outside.

In the present embodiment, it is also possible to convey an unprocessed wafer from the load chamber (not shown schematically) to the process module 52 a by the first end conveyance chamber 54 a while conveying a wafer having been subjected to the processing in the process module 52 a to the process module 52 c by the intermediate conveyance chamber 54 b and processing it, and therefore, the processing speed of the device as a whole is increased.

In the present embodiment, it may also be possible to configure the conveyance mechanisms 55 a to 55 c so as to be capable of conveying at least two wafers at the same time. For example, the conveyance mechanisms 55 a to 55 c are each configured as a wafer holding means having two arms capable of independent operation. With this structure, it is possible, for example, to convey an unprocessed wafer from the load lock chamber 51 to the first process module 52 a using one arm of the conveyance mechanism 55 a and at the same time to convey a processed wafer from the second process module 52 b to the load lock chamber 51 using the other arm of the conveyance mechanism 55 a. Because of this, the throughput of the device as a whole is improved.

The inline-type wafer conveyance device in the present embodiment does not require a transfer mechanism, such as the carrier 23 and the roller 25 shown in FIG. 2. Because of this, particles are unlikely to be generated during the period of conveyance of a wafer. Further, the wafer conveyance device has a simpler structure and a smaller footprint compared to the conveyance device that uses a buffer chamber as shown in FIG. 3. Furthermore, it is not necessary for robots to directly deliver a wafer between them, and therefore, a wafer conveyance device having high reliability can be realized. In addition, the wafer conveyance device has a very simple structure and a small footprint compared to the cluster-type conveyance device shown in FIG. 4. As described above, according to the present invention, it is possible to comprehensively solve the above-mentioned problems of the prior art.

First Embodiment

FIG. 6 is a plan view of an embodiment of the inline-type wafer conveyance device according to the present invention. A wafer conveyance device 60 comprises a FOUP (front opening unified pod) 61 including a load chamber 61 a and an unload chamber 61 b instead of the load lock chamber 51 in FIG. 5. The FOUP 61 is connected to a first end conveyance chamber 64 a. It is of course possible to use the load lock chamber 51 also instead of the FOUP 61.

The wafer conveyance device 60 comprises, in addition to the FOUP 61 described above, the first end conveyance chamber 64 a, four sets of a pair of process modules (first process module 62 a and second process module 62 b, third process module 62 c and fourth process module 62 d, fifth process module 62 e and sixth process module 62 f, and seventh process module 62 g and eighth process module 62 h), intermediate conveyance chambers 64 b, 64 c and 64 d, and a second end conveyance chamber 64 e. As in FIG. 5, each component is connected via a gate valve 66. By providing a gate valve, it is possible to reduce the number of foreign substances that enter mixedly between the process modules.

The basic relationship of connection between each component in the wafer conveyance device 60 is the same as that of the wafer conveyance device 50 and characterized by providing the second end conveyance chamber 64 e, which is connected to the opposite side of the load lock chamber 51 of the last set of process modules (the seventh process module 62 g and the eighth process module 62 h in FIG. 6). The second end conveyance chamber 64 e is located at the end part of the wafer conveyance device 60.

In addition to the characteristic, the wafer conveyance device 60 is noticeably characterized in the shape of each component. As shown in FIG. 6, each of the intermediate conveyance chambers 64 b to 64 d has, preferably, substantially a square plane shape when viewed from above. For example, the plane shape of each intermediate conveyance chamber is substantially a square and each intermediate conveyance chamber is disposed so that each side of the square forms an angle of about 45° with respect to the longitudinal direction (horizontal direction in FIG. 6) of the wafer conveyance device 60. The intermediate conveyance chambers 64 b to 64 d each have four side surfaces in the direction perpendicular to the plane of the paper in FIG. 6 and each side surface is connected to each neighboring process module via the gate valve 66. For example, each side surface may include a horizontal slit to let a wafer pass.

The first end conveyance chamber 64 a has, in addition to the side surface connected to the FOUP 61, has two side surfaces for connection to each of the first process module 62 a and the second process module 62 b belonging to the neighboring set of a pair of process modules. These two side surfaces may include a horizontal slit to let a wafer pass. Further, these two side surfaces are configured so as to form an angle to arrange the first end conveyance chamber 64 a, the first and second process modules 62 a and 62 b, and the first intermediate conveyance chamber 64 b with no extra gap left in between. Preferably, the angle is about 90° because the first intermediate conveyance chamber 64 b has substantially a square plane shape.

Each of the process modules 62 a to 62 h has two side surfaces for connection to the neighboring first end conveyance chamber 64 a, the intermediate conveyance chambers 64 b to 64 d, or the second end conveyance chamber 64 e. These two side surfaces may include a horizontal slit to let a wafer pass. Further, these two side surfaces are configured so as to form an angle in order to arrange each conveyance chamber and each process module with no extra gap left in between. For example, the angle is about 90°. The process modules 62 a to 62 h do not necessarily have substantially a square plane shape and may have various plane shapes, such as reference numeral 62 e shown in FIG. 6.

The second end conveyance chamber 64 at least has two side surfaces for connection to the two process modules 62 g and 62 h belonging to the neighboring set of a pair of process modules. These two side surfaces may include a horizontal slit to let a wafer pass. Further, these two side surfaces are configured so as to form an angle in order to arrange the second end conveyance chamber 62 e and the two neighboring process modules 62 g and 62 h with no extra gap left in between. For example, the angle is about 90°.

It is possible to configure the conveyance chamber and the process module so as to have various plane shapes, such as a square and a circle, and the side surface with the above-described structure is not necessarily required. It is only required to design the structure so that the pair of process modules (for example, 62 a and 62 b in FIG. 6) belonging to each set of process modules is connected to one of the neighboring conveyance chambers (for example, 65 a in FIG. 6) via one of two gate valves the directions of which are perpendicular to each other and connected to the other neighboring conveyance chamber (for example, 65 b in FIG. 6) via the other gate valve, respectively.

The process modules 62 a to 62 h are configured so as to be capable of performing, for example, etching processing, physical vapor deposition (PVD) processing, chemical vapor deposition (CVD) processing, thermal processing, alignment (positioning) processing, etc. As shown in FIG. 6, it is possible to configure the wafer conveyance device in the present embodiment so as to comprise a number of conveyance chambers while keeping its footprint small compared to the prior art by arranging the conveyance chambers and process modules having a compact structure with no gap left in between.

At the time of processing in each process module, a wafer is placed on a stage within the process module. In the present embodiment, each conveyance chamber only moves a wafer from a certain process module to the next process module, and does not require a complicated wafer conveyance. Further, it is not indispensable to dispose a buffer chamber for once placing a wafer along the way of the conveyance path.

In the present embodiment, it is also possible to convey an unprocessed wafer from the load chamber 61 a to the process module 62 a by the first end conveyance chamber 64 a while conveying a wafer having been subjected to the processing in the process module 62 a to the process module 62 c by the intermediate conveyance chamber 65 b and processing it, and therefore, the processing speed of the device as a whole is increased.

Then, it may also be possible to configure each conveyance mechanism as a robot having two arms capable of independent operation and at the same time to configure it so as to be capable of simultaneously conveying at least two wafers. With such a structure, it is possible for the wafer conveyance device in the present embodiment to achieve higher throughput compared to, for example, the conventional wafer conveyance device shown in FIG. 4.

With the structure as shown in FIG. 6, the maximum number n of process modules that can be arranged in the wafer conveyance device can be expressed as n=2 (m−1). Here, m is the number of conveyance chambers (first end conveyance chamber, intermediate conveyance chambers, and second end conveyance chamber).

A plan view of another structure example of the wafer conveyance device according to the present embodiment is shown in FIG. 7. A wafer conveyance device 70 comprises a load lock chamber 71, a first end conveyance chamber 74 a, one intermediate conveyance chamber 74 b, a second end conveyance chamber 74 c, and first to fourth process modules 72 a to 72 d.

The load lock chamber 71 includes a load chamber 71 a, an unload chamber 71 b, a conveyance mechanism 71 c, a first buffer chamber 71 d and a second buffer chamber 72 e. The first end conveyance chamber 74 a has substantially a square plane shape and has, in addition to first and second side surfaces connected to the process modules 72 a and 72 b, third and fourth side surfaces connected to the first and second buffer chambers 71 d and 71 e of the load lock chamber 71, respectively. An unprocessed wafer is carried into the load chamber 71 a from outside and placed in the buffer chamber 71 d by the conveyance mechanism 71 c. The wafer is conveyed from the buffer chamber 71 d to the first process module 72 a using a conveyance mechanism 75 a of the first end conveyance chamber 74 a. After that, the processed wafer having been conveyed and subjected to processing in a manner similar to that in FIG. 6, is carried into the second buffer chamber 71 e from the second process module 72 b by the conveyance mechanism 75 a and further, is conveyed to the unload chamber 71 b by the conveyance mechanism 71 c within the load lock chamber 71 and carried out to outside. The wafer conveyance device 70 also exhibits the same effect as that of the wafer conveyance device 60 in FIG. 6.

Even if the first end conveyance chamber 74 a has a circular plane shape or a plane shape other than a square, it is possible to apply the load lock chamber 71 in FIG. 6. In this case, the first end conveyance chamber 74 a is connected to, for example, each of the first and second buffer chambers via two gate valves having directions perpendicular to each other.

A structure example when a specific process is performed in a structure similar to that of the wafer conveyance device 60 in FIG. 6 is shown in FIG. 8. In FIG. 8, each wafer passes through various process modules 82 a to 82 h and returns to a FOUP 81 after having been subjected to processing. As an example, in FIG. 8, the first process module 82 a is a thermal process module for cleaning the contamination of a wafer and the third process module 82 c is an etching module for removing oxide on a wafer. Further, the fifth process module 82 e is a PVD module having a cathode electrode 87 holding four targets for forming films of different materials on a wafer by simultaneous sputtering or film formation processes at least in order. The seventh process module 82 g and the eighth process module 82 h are each a PVD module having a single target. The sixth process module 82 f and the second process module 82 b are each a PVD module having two targets. The fourth process module 82 d is a buffer module for aligning (positioning) a wafer or performing thermal processing.

As shown schematically, each process module has a different size, however, its two side surfaces to be connected to neighboring conveyance chambers are configured so as to enable an arrangement in which there is no extra gap left between the side surfaces and the conveyance chambers. These side surfaces may each include a slit to let a wafer pass during the period of conveyance of a wafer. Preferably, the stage within each process module is also arranged at the same position in the vertical direction with respect to these slits. Due to this, it is made easier to convey a wafer by a conveyance mechanism. As to a large-sized process module, it may also be possible to configure at least one neighboring conveyance chamber so as to be smaller in size than the other neighboring conveyance chambers.

In order to obtain high throughput, it is necessary to make the processing time in each process module substantially the same. When the tact time required to process one wafer throughout the whole of a wafer conveyance device 80 is 36 seconds, the throughput of the wafer conveyance device 80 is 100 pph and 100 wafers can be processed in one hour. When the tact time is 12 seconds, the throughput is 300 pph and 300 wafers can be processed in one hour.

Further, if each conveyance chamber is configured so as to have two independent arms capable of simultaneously conveying two wafers, the conveyance time can be reduced further, and therefore, the throughput is improved. In this case, for example, while a wafer is conveyed from the first process module 82 a to the third process module 82 c by one arm of the conveyance mechanism within a first intermediate conveyance chamber 84 b, another wafer is conveyed from the fourth process module 82 d to the fourth process module 82 b by the other arm within the first intermediate conveyance chamber 84 b.

The wafer conveyance device 80 shown in FIG. 8 uses a variety of process modules compared to the example shown in FIG. 6 and is capable of continuously performing eight kinds of processing regardless of the shape of the process module and exhibits a unique effect that throughput is high. If the number of process modules and conveyance chambers is increased further, it is possible to continuously perform more kinds of processing on a wafer.

A structure example in which the number of process modules and intermediate conveyance chambers is increased in a structure similar to that of the wafer conveyance device 70 is shown in FIG. 9. As described already, it is possible to use a variety of process modules, such as 92 a in FIG. 9. The maximum number n of process modules that can be arranged is expressed as n=2 (m−1). Here, m is the number of conveyance chambers including a conveyance chamber 91 f within a FOUP 91.

In a wafer conveyance device 90 in FIG. 9, there is a space 98 a between buffer chambers 91 d and 91 e, and therefore, it is possible to add a feature, such as aligner, to this part.

An example that specifically represents a structure similar to that of the wafer conveyance device 60 in FIG. 6 is shown in FIG. 10. A wafer conveyance device 100 comprises 10 process modules having two or four cathode electrodes 107 that hold various target materials. Further, each conveyance chamber has a double arm structure in which two arms 105 a and 105 b are included. A wafer is conveyed from a load chamber 101 a to an unload chamber 101 b as shown by a dotted line with arrow in the figure and processed in each process module. The double arm structure makes it possible to convey, while conveying a wafer from a first process module 102 a to a third process module 102 c using the one arm 105 a, another wafer from a fourth process module 102 d to a second process module 102 b. Because of this, the throughput of the wafer conveyance device 100 as a whole is increased.

FIG. 11 shows a case where an actual process is performed using an inline-type wafer conveyance device 110 in the present embodiment, which resembles that illustrated in FIG. 7. It is supposed to form an insulating film, such as LaHfOx and LaAlOx, used in a semiconductor device on a wafer.

First, after an unprocessed wafer is carried into a load chamber 111 a from the outside (atmosphere side) of the load chamber 111 a, the load chamber 111 a is evacuated using an evacuation mechanism (not shown schematically). Next, the unprocessed wafer is carried into a first process module 112 a using a first wafer holding means 115 a constituting a conveyance mechanism within a first end conveyance chamber 114 a and degassing processing of the wafer or pre-cleaning of the wafer is performed. Next, within a third process module 112 c, an LaHfOx film, an LaAlOx film, or a laminated film of these is formed on the wafer by RF sputtering. For example, the third process module 112 c internally includes a cathode electrode that holds a target material LaHfOx or LaAlOx. When a gas, for example, argon (Ar) gas, is introduced into the third process module 112 c through a gas introduction inlet (not shown schematically) and further, RF power is applied to the above-mentioned cathode electrode, plasma is generated within the process module 112 c. Ar ions etc. drawn out from the plasma collide with the target and a desired film is formed on the wafer as sputtered particles. If necessary, after UHV annealing is performed on the wafer within a fourth process module 112 d and then predetermined processing is performed within a second process module 112 b, the finally processed wafer is carried out from an unload chamber 111 b.

FIG. 12 shows a case where an actual process is performed after adding further a fifth process module 122 e and a sixth process module 122 f and one intermediate conveyance chamber to the inline-type wafer conveyance device illustrated in FIG. 11. A flow of procedure for forming a wiring Al film including via hole filling used in a memory system device is supposed. The film structure is designed as, for example, Ti (20 nm)/TiN (60 nm)/Seed-Al (200 nm)/Fill-Al (450 nm).

First, an unprocessed wafer is carried into a load chamber 121 a from outside (atmosphere side) and the load chamber 121 a is evacuated. Next, after the unprocessed wafer is carried into a first process module 122 a, a degas processing of the wafer is performed and pre-cleaning of the wafer surface is performed within a third process module 122 c. Next, the wafer is carried into the fifth process module 122 e, and a titanium film (for example, 20 nm) and a TiN film (for example, 60 nm) are formed sequentially. Next, using a conveyance mechanism 125 a within a second end conveyance chamber 124 d, the wafer is carried into the sixth process module 122 f from the fifth process module 122 e and a Seed-Al film (for example, 200 nm) is formed. Next, the wafer is carried into a fourth process module 122 d from the sixth process module 122 f and a Fill-Al film (for example, 450 nm) is formed. Next, the wafer is carried into a second process module 122 b from the fourth process module 122 d and after having cooled down, the above-mentioned wafer is carried out from an unload chamber to outside (atmosphere side). In FIG. 12, the Ti film having a thickness of 20 nm is formed in 122 e and the Seed-Al film having a thickness of 200 nm is formed in 122 f, however, by preparing the two process modules 122 e, it is also possible to form a Ti film having a thickness of 10 nm in the first process module and form a Ti film having a thickness of 10 nm in the second process module, and then form a Ti film having a total thickness of 20 nm. For example, if the film formation in 122 e requires two minutes and the film formation in 122 f requires one minute, by preparing the two chambers 122 e, it is possible to eliminate a wafer that waits for processing and the throughput can be increased as a result.

FIG. 13 shows a case where an actual process is performed using an inline-type wafer conveyance device 130 similar to that in FIG. 12. A supposed process is a processing/film formation continuous process for forming a cover film by CVD after etching a magnetic laminated film without exposing it to the atmosphere. For example, the structure of a film to be etched is PR/Ta/TMR. An unprocessed wafer carried in from outside is conveyed from a load chamber 131 a to a first process module 132 a. First, if necessary, trimming of a first resist is performed in the first process module 132 a and reactive ion etching (RIE) of a Ta film is performed with a CF₄-based gas using the resist as a mask in a third process module 132 c. Further, the resist is removed in the same module 132 c for the purpose of resist peeling. After the wafer is conveyed to a fifth process module 132 e, RIE is performed in a CH₃OH process on a magnetic laminated film having a TMR structure in the module. Further, the wafer is conveyed to a sixth process module 132 f and ion beam etching (IBE) is performed to clean the surface after RIE with CH₃OH. After the wafer that has been subjected to IBE is conveyed continuously in a vacuum, a nitride film, an oxide film, a carbon film, etc., are formed by the plasma chemical vapor deposition (CVD) or remote plasma CVD in a fourth process module 132 d. Furthermore, if necessary, a predetermined process is performed in a second process module 132 b.

FIG. 14 shows a case where an actual process is performed using an inline-type wafer conveyance device 140 as illustrated in FIG. 10. A flow of procedure for forming a TMR laminated film in a storage cell part used in a magnetic resistance random access memory (MRAM) is supposed. The film structure is designed as, for example, Ta (20 nm)/Ru (5 nm)/IrMn (7 nm)/CoFe (2.5 nm)/Ru (0.9 nm)/CoFeB (3 nm)/MgO (1 nm)/CoFeb (3 nm)/Ta (2 nm)/Ru (10 nm)/Ta (30 nm).

After etching of a wafer is performed in a first process module 142 a, a Ta film (for example, 20 nm) is formed in a third process module 142 c, a Ru film (for example, 5 nm) in a fifth process module 142 e, an IrMn film (for example, 7 nm) and a CoFe film (for example, 2.5 nm) in a seventh process module 142 g, and an Ru film (for example, 0.9 nm) and a CoFeB film (for example, 3 nm) in a ninth process module 142 i, respectively, by DC sputtering. Further, in a tenth process module 142 j, an MgO film (for example, 1 nm) is formed by RF sputtering. Furthermore, in an eighth process module 142 h, a CoFeB film (for example, 3 nm) and a Ta film (for example, 2 nm) are formed, a Ru film (for example, 10 nm) in a sixth process module 142 f, and a Ta film (for example, 30 nm) in a fourth process module 142 d, respectively, by DC sputtering. Further, if necessary, predetermined processing is performed in a second process module 142 b. In the above-mentioned process, the MgO film is formed by RF sputtering. In FIG. 14, the Ta film having a thickness of 20 nm is formed in 142 c and the Ru film having a thickness of 5 nm is formed in 142 e, however, by preparing the two process modules 142 c, it is also possible to form a Ta film having a thickness of 10 nm in the first process module and form a Ta film having a thickness of 10 nm in the second process module, and then form a Ta film having a total thickness of 20 nm. For example, if the film formation in 142 c requires two minutes and the film formation in 142 e requires one minute, by preparing the two chambers 142 c, it is possible to eliminate a wafer that waits for processing and the throughput can be increased as a result.

In FIG. 14, the first process module 142 a is an etching module.

FIG. 15 shows a case where an actual process is performed using an inline-type wafer conveyance device 150 similar to that in FIG. 14. A flow of procedure for forming a TMR laminated film in a storage cell part used in an MRAM is supposed. The film structure is designed as, for example, Ta (20 nm)/Ru (5 nm)/IrMn (7 nm)/CoFe (2.5 nm)/Ru (0.9 nm)/CoFeB (3 nm)/MgO (1 nm)/CoFeB (3 nm)/Ta (2 nm)/Ru (10 nm)/Ta (30 nm).

After etching of a wafer is performed in a first process module 152 a, a Ta film (for example, 20 nm) is formed in a third process module 152 c, an Ru film (for example, 5 nm) in a fifth process module 152 e, an IrMn film (for example, 7 nm) and a CoFe film (for example, 2.5 nm) in a seventh process module 152 g, and an Ru film (for example, 0.9 nm) and a CoFeB film (for example, 3 nm) in a ninth process module 152 i, respectively. Further, in a tenth process module 152 j, an Mg film (for example, 1 nm) is formed and the Mg film is oxidized in an eighth process module 152 h. Then, in a sixth process module 152 f, a CoFeB film (for example, 3 nm) and a Ta film (for example, 2 nm) are formed, an Ru film (for example, 10 nm) in a fourth process module 152 d, and a Ta film (for example, 30 nm) in a second process module 152 b, respectively. In the above-mentioned process, the Mg film is formed by DC sputtering and then the MgO film is formed in the oxidation process. In FIG. 15, the Ta film having a thickness of 20 nm is formed in 152 c and the Ru film having a thickness of 5 nm in 152 e, however, by preparing the two process modules 152 c, it is also possible to form a Ta film having a thickness of 10 nm in the first process module and form a Ta film having a thickness of 10 nm in the second process module, and then form a Ta film having a total thickness of 20 nm. For example, if the film formation in 152 c requires two minutes and the film formation in 152 e requires one minute, by preparing the two chambers 152 c, it is possible to eliminate a wafer that waits for processing and the throughput can be increased as a result.

In FIG. 15, the first process module 152 a is an etching module and the eighth process module 152 h is an oxidation module.

FIG. 16 shows a case where an actual process is performed using an inline-type wafer conveyance device 160 similar to that in FIG. 14. A flow of procedure for forming a CrOx/AlOx laminated film, a CrOx single layer film, or an AlOx single layer film, which is an insulating film used in a semiconductor device, is supposed. A wafer having been subjected to degassing processing in a first process module 162 a is conveyed to a third process module 162 c and after a Cr film is formed on the wafer, a CrOx film is formed in an oxidation process in a fifth process module 162 e. The formation of an AlOx film is also the same, that is, after an Al film is formed in a tenth process module 162 j, an AlOx film is formed in an oxidation process in an eighth process module 162 h. In accordance with a required film thickness, by preparing a plurality of sets (not shown schematically) of Cr film formation modules (162 c, 162 g) and oxidation modules (162 e, 162 i) as shown in FIG. 16, it is possible to form the CrOx film without return conveyance. Similarly, in accordance with a required film thickness, by preparing a plurality of sets (not shown schematically) of Al film formation modules (162 j, 162 f) and oxidation modules (162 h, 162 d); it is possible to form the AlOx film without return conveyance. After the formation of the desired CrOx/AlOx laminated film, the CrOx single layer film, or the AlOx single layer film is completed, annealing processing is performed in a second process module 162 b.

In FIG. 16, the first process module 162 a is a degas module, the fifth process module 162 e, the ninth process module 162 i, the eighth process module 162 h and the fourth process module 162 d are each an oxidation module, and the second process module 162 b is an annealing module.

FIG. 17 shows a case where an actual process is performed using an inline-type wafer conveyance device 170 similar to that in FIG. 14. A flow of procedure for forming a CrOx/AlOx laminated film, a CrOx single layer film, or an AlOx single layer film, which is an insulating film used in a semiconductor device, is supposed. A wafer having been subjected to degassing processing in a first process module 172 a is conveyed to a third process module 172 c and after a Cr film is formed on the wafer, a CrOx film is formed in an oxidation process in a fifth process module 172 e. The formation of an AlOx film is the same, that is, after an Al film is formed in a tenth process module 172 j, an AlOx film is formed in an oxidation process in an eighth process module 172 h. In accordance with a required film thickness, a plurality of sets (not shown schematically) of Cr film formation modules (172 c, 172 g) and oxidation modules (172 e, 172 i) is prepared and film formation and oxidation are repeated by return conveyance. When a CrOx film having a thickness of 20 nm is formed, after a Cr film having a thickness of 1 nm is formed in the Cr film formation module, the Cr film is oxidized in the oxidation module to form a CrOx film having a thickness of 2 nm, and then this set of tasks is repeated ten times and thus a CrOx film having a thickness of 20 nm is formed. The formation of an AlOx film is the same. After the formation of the desired CrOx/AlOx laminated film, the CrOx single layer film, or the AlOx single layer film is completed, annealing processing is performed in a second process module 172 b.

In FIG. 17 also, the first process module 172 a is a degas module, the fifth process module 172 e, the ninth process module 172 i, the eighth process module 172 h and a fourth process module 172 d are each an oxidation module and the second process module 172 b is an annealing module.

FIG. 18 shows a case where an actual process is performed using an inline-type wafer conveyance device 180 similar to that in FIG. 14. A flow of procedure for forming an LaAlOx film, which is an insulating film used in a semiconductor device, is supposed. After an LaAl alloy film is formed by co-sputtering of La and Al in a third process module 182 c, an LaAlOx film is formed in an oxidation process in a fifth process module 182 e. Further, after a LaAl film is formed by co-sputtering of La and Al in a seventh process module 182 g, a LaAlOx layer is formed in an oxidation process in a ninth process module 182 i. Similarly, film formation (tenth process module 182 j) and oxidation (eighth process module 182 h), film formation (sixth process module 182 f) and oxidation (fourth process module 182 d) are repeated. In order to form a desired LaAlOx film, the above-mentioned set is repeated.

In FIG. 18 also, a first process module 182 a is a degas module, the fifth process module 182 e, the ninth process module 182 i, the eighth process module 182 h and the fourth process module 182 d are each an oxidation module, and a second process module 182 b is an annealing module.

FIG. 19 shows a case where an actual process is performed using an inline-type wafer conveyance device 190 that has the same structure illustrated in FIG. 14 except in that the number of process modules is eight and the number of intermediate conveyance chambers is three. A flow of procedure for forming a wiring Al film including via whole embodiment used in a memory system device is supposed. The film structure is designed as, for example, Ti (20 nm)/TiN (60 nm)/Seed-Al (200 nm)/Fill-Al (450 nm)/TiN (100 nm). First, an unprocessed wafer is carried into a load chamber 191 a from outside (atmosphere side) and the load chamber 191 a is evacuated. Next, after the unprocessed wafer is carried into a first process module 192 a, the wafer is subjected to degassing processing and pre-cleaning of the wafer surface is performed within a third process module 192 c. Next, the wafer is carried into a fifth process module 192 e, and a titanium film (for example, 20 nm) and a TiN film (for example, 60 nm) are formed sequentially. Next, the wafer is carried into a seventh process module 192 g from the fifth process module 192 e and a Seed-Al film (for example, 200 nm) is formed. Next, the wafer is carried into an eighth process module 192 h from the seventh process module 192 g using a conveyance mechanism 195 a within an end conveyance chamber 194 e and a Fill-Al film (for example, 450 nm) is formed. Next, the wafer is carried into a sixth process module 192 f from the eighth process module 192 h and after the above-mentioned wafer is cooled down, an ARC Cap film of TiN is formed in a fourth process module 192 d or a second process module 192 b and carried out from an unload chamber 191 b to outside (atmosphere side). In FIG. 19, the Ti film having a thickness of 20 nm is formed in 192 e and the Seed-Al film having a thickness of 200 nm is formed in 192 g, however, by preparing the two process modules 192 e, it is also possible to form a Ti film having a thickness of 10 nm in the first process module and form a Ti film having a thickness of 10 nm in the second process module, and then form a Ti film having a total thickness of 20 nm. For example, if the film formation in 192 e requires two minutes and the film formation in 192 g requires one minute, by preparing the two process modules 192 e, it is possible to eliminate a wafer that waits for processing and the throughput can be increased as a result.

In FIG. 19, the first process module 192 a is a degas module, the third process module 192 c is a pre-cleaning module and the sixth process module 192 f is a cooling module.

In the embodiments shown in FIGS. 10 to 19, each process module is shown to have a double arm structure, however, it is also possible for each process module to have a single arm structure.

Table 1 and FIG. 20 show a relationship between throughput and processing time of a wafer conveyance device when the second end conveyance chamber is used as in the wafer conveyance device of the present invention and when the second end conveyance chamber is not used. In Table 1, n_(P) represents the number of process modules comprised by a wafer conveyance device, t_(P) the processing time required by one process module, and t_(R) the conveyance time required by one conveyance chamber to convey a wafer between process modules located ahead and behind. The maximum time in Table 1 is the maximum processing time in the processes in all of the process modules. The maximum time when the second end conveyance chamber is used is calculated as a sum of t_(P) and t_(R) and the maximum time when the second end conveyance chamber is not used as a sum of t_(P) and twice t_(R). “Wph (wafer per hour)” represents the number of wafers to be processed per hour.

Table 1 shows throughput when n_(P)=6 and t_(R)=2 are assumed, and the process time t_(P) is set to various values when the second end conveyance chamber exists and when not. A graph in which the vertical axis represents throughput and the horizontal axis represents process time is shown in FIG. 20. When the process time is short, a difference between when the second end conveyance chamber exists and when not is remarkable and it can be seen that the wafer processing performance per unit time of a wafer conveyance device is increased by using the second end conveyance chamber as in the present invention.

TABLE 1 With 2nd end Without 2nd end conveyance chamber conveyance chamber t_(P) Max. time Throughput Max. time Throughput n_(p) (sec) t_(R) (sec) (sec) (wph) (sec) (wph) 6 0 2 2 1800.0 4 900.0 6 1 2 3 1200.0 5 720.0 6 2 2 4 900.0 6 600.0 6 3 2 5 720.0 7 514.3 6 4 2 6 600.0 8 450.0 6 5 2 7 514.3 9 400.0 6 6 2 8 450.0 10 360.0 6 7 2 9 400.0 11 327.3 6 8 2 10 360.0 12 300.0 6 9 2 11 327.3 13 276.9 6 10 2 12 300.0 14 257.1 6 11 2 13 276.9 15 240.0 6 12 2 14 257.1 16 225.0 6 13 2 15 240.0 17 211.8 6 14 2 16 225.0 18 200.0 6 15 2 17 211.8 19 189.5 6 16 2 18 200.0 20 180.0 6 17 2 19 189.5 21 171.4 6 18 2 20 180.0 22 163.6 6 19 2 21 171.4 23 156.5 6 20 2 22 163.6 24 150.0 6 21 2 23 156.5 25 144.0 6 22 2 24 150.0 26 138.5 6 23 2 25 144.0 27 133.3 6 24 2 26 138.5 28 128.6 6 25 2 27 133.3 29 124.1 n_(p) = Number of process modules t_(P) = Process time t_(R) = Conveyance time 

1. An inline-type wafer conveyance device comprising: a load lock chamber for carrying in an unprocessed wafer from outside and carrying out a processed wafer to the outside; a first end conveyance chamber connected to the load lock chamber; at least one intermediate conveyance chamber; a plurality of sets of a pair of process modules provided adjacent to each other and capable of independent processing, each set of process modules comprising a pair of process modules; and a second end conveyance chamber located at the end part of the inline-type wafer conveyance device, the end part being the opposite side to the load lock chamber, wherein a set of process modules is arranged one by one between the first end conveyance chamber and an intermediate conveyance chamber, between intermediate conveyance chambers when more than one intermediate conveyance chamber are provided, and between an intermediate conveyance chamber and the second end conveyance chamber, respectively.
 2. An inline-type wafer conveyance device according to claim 1, wherein the first end conveyance chamber, the intermediate conveyance chamber, and the second end conveyance chamber each have a conveyance mechanism capable of simultaneously conveying at least two wafers.
 3. An inline-type wafer conveyance device according to claim 1, wherein: the first end conveyance chamber and the second end conveyance chamber each have at least one conveyance mechanism and at least first and second side surfaces perpendicular to each other; each of the intermediate conveyance chambers has at least one conveyance mechanism, substantially a square plane shape, and four side surfaces; each of the process modules has at least first and second side surfaces perpendicular to each other; the first and second side surfaces of the first end conveyance chamber are connected to the first side surface of one of the process modules constituting the first set of process modules and to the first side surface of the other process module, respectively; the first and second side surfaces of each intermediate conveyance chamber are connected to the second side surface of one of the process modules of the set of process modules located immediately ahead and to the second side surface of the other process module, respectively, and the third and fourth side surfaces of each intermediate conveyance chamber are connected to the first side surface of one of the process modules of the set of process modules located immediately behind and to the first side surface of the other process module, respectively; the first and second side surfaces of the second end conveyance chamber are connected to the second side surface of one of the process modules of the set of process modules located immediately ahead and to the second side surface of the other process module, respectively; and the second end conveyance chamber is located at the end part of the inline-type wafer conveyance device.
 4. An inline-type wafer conveyance device according to claim 3, wherein: the first and second side surfaces of the first end conveyance chamber, the first to fourth side surfaces of the intermediate conveyance chamber, the first and second side surfaces of the second end conveyance chamber, and the first and second side surfaces of the process module each include a horizontal slit to let a wafer pass; and the process module has a stage for placing a wafer.
 5. An inline-type wafer conveyance device according to claim 1, wherein: each of the first end conveyance chamber and the second end conveyance chamber has at least one conveyance mechanism and each of the intermediate conveyance chambers has at least one conveyance mechanism; and the pair of process modules belonging to each of the sets of process modules is connected to one of neighboring conveyance chambers via one of two gate valves the directions of which are perpendicular to each other and to the other neighboring conveyance chamber via the other gate valve.
 6. An inline-type wafer conveyance device according to claim 1, wherein when the total number of the first end conveyance chamber, the intermediate conveyance chambers and the second end conveyance chamber is m, the number of the process modules n is expressed as n=2 (m−1) at the maximum.
 7. An inline-type wafer conveyance device according to claim 1, wherein the load lock chamber, the first end conveyance chamber, the intermediate conveyance chamber, the process module and the second end conveyance chamber are connected via gate valves.
 8. An inline-type wafer conveyance device according to claim 3, wherein: the load lock chamber includes a conveyance mechanism and first and second buffer chambers; and the first end conveyance chamber has substantially a square plane shape and four side surfaces, and the third and fourth side surfaces of the first end conveyance chamber are connected to the first and second buffer chambers, respectively.
 9. An inline-type wafer conveyance device according to claim 5, wherein: the load lock chamber includes a conveyance mechanism and first and second buffer chambers; and the first end conveyance chamber is connected to the first and second buffer chambers, respectively.
 10. An inline-type wafer conveyance device according to claim 8, wherein: an unprocessed wafer is carried into one of the process modules connected to the first end conveyance chamber from the first buffer chamber by the conveyance mechanism of the first end conveyance chamber; and a processed wafer is carried out to the second buffer chamber from the other process module connected to the first end conveyance chamber by the conveyance mechanism of the first end conveyance chamber.
 11. An inline-type wafer conveyance device according to claim 8, wherein a space is provided between the first buffer chamber and the second buffer chamber.
 12. An inline-type wafer conveyance device according to claim 1, wherein: the number of the process modules is six; and the conveyance time required for the one conveyance chamber to convey a wafer between the process modules located ahead and behind is two seconds and the maximum process time in each process module is ten seconds or less.
 13. An inline-type wafer conveyance device according to claim 9, wherein: an unprocessed wafer is carried into one of the process modules connected to the first end conveyance chamber from the first buffer chamber by the conveyance mechanism of the first end conveyance chamber; and a processed wafer is carried out to the second buffer chamber from the other process module connected to the first end conveyance chamber by the conveyance mechanism of the first end conveyance chamber.
 14. An inline-type wafer conveyance device according to claim 9, wherein a space is provided between the first buffer chamber and the second buffer chamber.
 15. An inline-type wafer conveyance device according to claim 10, wherein a space is provided between the first buffer chamber and the second buffer chamber. 